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Design and Implementation of Parameterized Convolutional encoder IP cores
Duan MQ(段茂强); Huang XL(黄晓莉)
作者部门工业控制网络与系统研究室
会议名称The 2nd International Conference on Electronics,Communications and Control (ICECC2012)
会议日期October 16-18, 2012
会议地点Zhoushan,China
会议主办者IEEE
会议录名称The 2nd International Conference on Electronics,Communications and Control (ICECC2012)
出版者IEEE Computer Society
出版地New York, USA
2012
页码1455-1458
产权排序1
ISBN号978-0-7695-4806-7
关键词Convolutional Encodes Parallel Computing Parameterized Ip Core
摘要The parameterized IP (Intellectual Property) core is flexible reused in the SoC (system on chip) development project, reduce the development period and occupy the appreciate market. The convolutional coder is a kind of good channel code, which is widely used in many fields such as deep space telecommunication, wireless communication and so on. In this paper, we design and implement general parameterized IP cores of convolutional encoder with SMIC 0.35μm CMOS technology, serial structure and parallel structure respectively. And analyze each of the power dissipation using Synopsys PTPX tool. The result shows the parallel circuit structure saves 14 percent power dissipation compared to that of serial circuit structure, with the same encode radio. Meanwhile, computing speed of parallel structure with 8-bit parallelism is 8 times than that of serial structure under the same clock frequency. Certainly, serial circuit structure has their particular characters such as easily realized and less resource consumption.
语种英语
文献类型会议论文
条目标识符http://ir.sia.cn/handle/173321/10236
专题工业控制网络与系统研究室
作者单位1.Lab of Industrial Control Network and System, Shenyang Institute of Automation, Chinese Academy of Sciences, Liaoning Shenyang, P. R. China
2.of Scientific & Technical Information of Liaoning Province, Liaoning Shenyang, P. R. China
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Duan MQ,Huang XL. Design and Implementation of Parameterized Convolutional encoder IP cores[C]//IEEE. New York, USA:IEEE Computer Society,2012:1455-1458.
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