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题名: Design and Implementation of Parameterized Convolutional encoder IP cores
作者: Duan MQ(段茂强) ; Huang XL(黄晓莉)
作者部门: 工业控制网络与系统研究室
会议名称: The 2nd International Conference on Electronics,Communications and Control (ICECC2012)
会议日期: October 16-18, 2012
会议地点: Zhoushan,China
会议主办者: IEEE
会议录: The 2nd International Conference on Electronics,Communications and Control (ICECC2012)
会议录出版者: IEEE Computer Society
会议录出版地: New York, USA
出版日期: 2012
页码: 1455-1458
ISBN号: 978-0-7695-4806-7
关键词: convolutional encodes ; parallel computing ; parameterized IP core
摘要: The parameterized IP (Intellectual Property) core is flexible reused in the SoC (system on chip) development project, reduce the development period and occupy the appreciate market. The convolutional coder is a kind of good channel code, which is widely used in many fields such as deep space telecommunication, wireless communication and so on. In this paper, we design and implement general parameterized IP cores of convolutional encoder with SMIC 0.35μm CMOS technology, serial structure and parallel structure respectively. And analyze each of the power dissipation using Synopsys PTPX tool. The result shows the parallel circuit structure saves 14 percent power dissipation compared to that of serial circuit structure, with the same encode radio. Meanwhile, computing speed of parallel structure with 8-bit parallelism is 8 times than that of serial structure under the same clock frequency. Certainly, serial circuit structure has their particular characters such as easily realized and less resource consumption.
产权排序: 1
内容类型: 会议论文
URI标识: http://ir.sia.cn/handle/173321/10236
Appears in Collections:工业控制网络与系统研究室_会议论文

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