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Design of (2, 1, N) parallel convolutional encodes for VLSI
Duan MQ(段茂强); Huang XL(黄晓莉)
Department工业控制网络与系统研究室
Conference Name2013 International Conference on Mechatronics and Industrial Informatics, ICMII 2013
Conference DateMarch 13-14, 2013
Conference PlaceGuangzhou, China
Author of SourceKorea Maritime University; Hong Kong Industrial Technology Research Centre
Source PublicationApplied Mechanics and Materials
PublisherTrans Tech Publications Ltd
Publication PlaceZurich-Durnten, Switzerland
2013
Pages2822-2827
Indexed ByEI ; CPCI(ISTP)
EI Accession number20132816489208
WOS IDWOS:000324348201255
Contribution Rank1
ISSN1660-9336
ISBN978-3-03785-694-9
KeywordCmos Integrated Circuits Encoding (Symbols) Information Science Low Power Electronics Parallel Architectures Parallel Processing Systems Shift Registers
AbstractThe characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes. © (2013) Trans Tech Publications, Switzerland.
Language英语
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Document Type会议论文
Identifierhttp://ir.sia.cn/handle/173321/12424
Collection工业控制网络与系统研究室
Recommended Citation
GB/T 7714
Duan MQ,Huang XL. Design of (2, 1, N) parallel convolutional encodes for VLSI[C]//Korea Maritime University; Hong Kong Industrial Technology Research Centre. Zurich-Durnten, Switzerland:Trans Tech Publications Ltd,2013:2822-2827.
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