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IP core design for parameterized (2, 1, N) convolutional encodes
Duan MQ(段茂强); Huang XL(黄晓莉); Yang ZJ(杨志家)
Department工业控制网络与系统研究室
Conference Name2013 2nd International Conference on Measurement, Instrumentation and Automation, ICMIA 2013
Conference DateApril 23-24, 2013
Conference PlaceGuilin, China
Author of SourceKorea Maritime University; Hong Kong Industrial Technology Research Centre; Inha University
Source PublicationApplied Mechanics and Materials
PublisherTrans Tech Publications Ltd
Publication PlaceZurich-Durnten, Switzerland
2013
Pages1463-1468
Indexed ByEI ; CPCI(ISTP)
EI Accession number20133516681633
WOS IDWOS:000328521200280
Contribution Rank1
ISSN1660-9336
ISBN978-3-03785-751-9
KeywordCmos Integrated Circuits Convolution Parameterization
AbstractIn this paper, we design and implement general parameterized IP (Intellectual Property) cores of convolutional encoder with SMIC 0.35μm CMOS technology, serial structure and parallel structure respectively. And analyze each of the power dissipation using Synopsys PTPX tool. The result shows the parallel circuit structure saves 14 percent power dissipation compared to that of serial circuit structure, with the same encode radio. Meanwhile, computing speed of parallel structure with 8-bit parallelism is 8 times than that of serial structure under the same clock frequency. Certainly, serial circuit structure has their particular characters such as easily realized and less resource consumption. © (2013) Trans Tech Publications, Switzerland.
Language英语
Citation statistics
Document Type会议论文
Identifierhttp://ir.sia.cn/handle/173321/12427
Collection工业控制网络与系统研究室
Recommended Citation
GB/T 7714
Duan MQ,Huang XL,Yang ZJ. IP core design for parameterized (2, 1, N) convolutional encodes[C]//Korea Maritime University; Hong Kong Industrial Technology Research Centre; Inha University. Zurich-Durnten, Switzerland:Trans Tech Publications Ltd,2013:1463-1468.
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