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Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence
Wang BP(王保坡); Du JS(杜劲松); Tian X(田星); Bi X(毕欣)
作者部门智能检测与装备研究室
会议名称2014 4th International Conference on Applied Mechanics, Materials and Manufacturing (ICA3M 2014)(Applied Mechanics and Materials)
会议日期August 23-24, 2014
会议地点Shenzhen, China
会议录名称Applied Mechanics and Materials
出版者Trans Tech Publications
出版地Zurich-Durnten, Switzerland
2014
页码1447-1453
收录类别EI ; CPCI(ISTP)
EI收录号20150300428918
WOS记录号WOS:000348385100290
产权排序1
ISSN号1662-7482
关键词Pcb Design Ddr3 Fly-by Leveling-free Source Synchronous
摘要For the requirements of different bus signals from high speed PCB with DDR3 components based on fly-by topology structure, coping strategies have been proposed respectively. For the address or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus and achieved good performance, combining with the rules of signal integrity. For the data bus, the timing sequence on source synchronous has been analyzed and the time margin was calculated. The reasonability of the design was verified through the simulation result with Cadence. 
语种英语
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文献类型会议论文
条目标识符http://ir.sia.cn/handle/173321/15346
专题智能检测与装备研究室
作者单位1.Shenyang Institute of Automation, Chinese Academy of Sciences, China
2.University of Chinese Academy of Sciences, China
3.Key Laboratory of Liaoning Province on Radar System and Application, China
推荐引用方式
GB/T 7714
Wang BP,Du JS,Tian X,et al. Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence[C]. Zurich-Durnten, Switzerland:Trans Tech Publications,2014:1447-1453.
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