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Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence
Wang BP(王保坡); Du JS(杜劲松); Tian X(田星); Bi X(毕欣)
Department智能检测与装备研究室
Conference Name2014 4th International Conference on Applied Mechanics, Materials and Manufacturing (ICA3M 2014)(Applied Mechanics and Materials)
Conference DateAugust 23-24, 2014
Conference PlaceShenzhen, China
Source PublicationApplied Mechanics and Materials
PublisherTrans Tech Publications
Publication PlaceZurich-Durnten, Switzerland
2014
Pages1447-1453
Indexed ByEI ; CPCI(ISTP)
EI Accession number20150300428918
WOS IDWOS:000348385100290
Contribution Rank1
ISSN1662-7482
KeywordPcb Design Ddr3 Fly-by Leveling-free Source Synchronous
AbstractFor the requirements of different bus signals from high speed PCB with DDR3 components based on fly-by topology structure, coping strategies have been proposed respectively. For the address or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus and achieved good performance, combining with the rules of signal integrity. For the data bus, the timing sequence on source synchronous has been analyzed and the time margin was calculated. The reasonability of the design was verified through the simulation result with Cadence. 
Language英语
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Cited Times:2[WOS]   [WOS Record]     [Related Records in WOS]
Document Type会议论文
Identifierhttp://ir.sia.cn/handle/173321/15346
Collection智能检测与装备研究室
Affiliation1.Shenyang Institute of Automation, Chinese Academy of Sciences, China
2.University of Chinese Academy of Sciences, China
3.Key Laboratory of Liaoning Province on Radar System and Application, China
Recommended Citation
GB/T 7714
Wang BP,Du JS,Tian X,et al. Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence[C]. Zurich-Durnten, Switzerland:Trans Tech Publications,2014:1447-1453.
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