中国科学院沈阳自动化研究所机构知识库
Advanced  
SIA OpenIR  > 智能检测与装备研究室  > 会议论文
题名: Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence
作者: Wang BP(王保坡); Du JS(杜劲松); Tian X(田星); Bi X(毕欣)
作者部门: 智能检测与装备研究室
会议名称: 2014 4th International Conference on Applied Mechanics, Materials and Manufacturing (ICA3M 2014)(Applied Mechanics and Materials)
会议日期: August 23-24, 2014
会议地点: Shenzhen, China
会议录: Applied Mechanics and Materials
会议录出版者: Trans Tech Publications
会议录出版地: Zurich-Durnten, Switzerland
出版日期: 2014
页码: 1447-1453
收录类别: EI ; CPCI(ISTP)
ISSN号: 1662-7482
关键词: PCB Design ; DDR3 ; Fly-by ; Leveling-free ; Source synchronous
摘要: For the requirements of different bus signals from high speed PCB with DDR3 components based on fly-by topology structure, coping strategies have been proposed respectively. For the address or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus and achieved good performance, combining with the rules of signal integrity. For the data bus, the timing sequence on source synchronous has been analyzed and the time margin was calculated. The reasonability of the design was verified through the simulation result with Cadence. 
产权排序: 1
内容类型: 会议论文
URI标识: http://ir.sia.cn/handle/173321/15346
Appears in Collections:智能检测与装备研究室_会议论文

Files in This Item: Download All
File Name/ File Size Content Type Version Access License
Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence.pdf(452KB)----开放获取View Download
Service
Recommend this item
Sava as my favorate item
Show this item's statistics
Export Endnote File
Google Scholar
Similar articles in Google Scholar
[Wang BP(王保坡)]'s Articles
[Du JS(杜劲松)]'s Articles
[Tian X(田星)]'s Articles
CSDL cross search
Similar articles in CSDL Cross Search
[Wang BP(王保坡)]‘s Articles
[Du JS(杜劲松)]‘s Articles
[Tian X(田星)]‘s Articles
Related Copyright Policies
Null
Social Bookmarking
Add to CiteULike Add to Connotea Add to Del.icio.us Add to Digg Add to Reddit
文件名: Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence.pdf
格式: Adobe PDF
所有评论 (0)
暂无评论
 
评注功能仅针对注册用户开放,请您登录
您对该条目有什么异议,请填写以下表单,管理员会尽快联系您。
内 容:
Email:  *
单位:
验证码:   刷新
您在IR的使用过程中有什么好的想法或者建议可以反馈给我们。
标 题:
 *
内 容:
Email:  *
验证码:   刷新

Items in IR are protected by copyright, with all rights reserved, unless otherwise indicated.

 

 

Valid XHTML 1.0!
Copyright © 2007-2016  中国科学院沈阳自动化研究所 - Feedback
Powered by CSpace