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题名: High bandwidth memory interface design based on DDR3 SDRAM and FPGA
作者: Wang BP(王宝坡); Du JS(杜劲松); Bi X(毕欣); Tian X(田星)
作者部门: 智能检测与装备研究室
会议名称: 12th International SoC Design Conference (ISOCC 2015)
会议日期: November 2-5, 2015
会议地点: Gyeongju, South Korea
会议录: 12th International SoC Design Conference (ISOCC 2015)
出版日期: 2015
页码: 253-254
收录类别: EI ; CPCI(ISTP)
关键词: Memory interface ; DDR3 ; FPGA ; IP ; High bandwidth
摘要: This work presented the high bandwidth memory interface design based on DDR3 SDRAM using external memory IP core provided by FPGA devices. The structure and configuration of IP core was introduced and the simulation on soft and hard IP was carried out with the access controller designed. The maximum transmission bandwidth of the memory interface based on the soft and hard IP respectively reached 19.2Gbps and 25.6Gbps. Finally, the reliability of the interface controller was verified by downloading the program to the DAQ board and observing the internal signals.
语种: 英语
产权排序: 1
WOS记录号: WOS:000380449100116
Citation statistics:
内容类型: 会议论文
URI标识: http://ir.sia.cn/handle/173321/17364
Appears in Collections:智能检测与装备研究室_会议论文

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Recommended Citation:
Wang BP,Du JS,Bi X,et al. High bandwidth memory interface design based on DDR3 SDRAM and FPGA[C]. 见:12th International SoC Design Conference (ISOCC 2015). Gyeongju, South Korea. November 2-5, 2015.
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文件名: High bandwidth memory interface design based on DDR3 SDRAM and FPGA.pdf
格式: Adobe PDF
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