This paper describes a methodology used for the implementation flow of a system on chip circuit containing a complex clock design. The clock generation module contained 2 clock sources and 11 generated clocks. Many of them have interactive relationship. and the 2 clock sources generate the internal clocks in various modes. It uses the combination of bottom-up strategy and top-down strategy to accomplish the clock generation module implementation first, and then finish the whole chip design. This methodology of the solution makes the whole structure of the design distinct, saves a lot of iterative time, and reduces chip power consumption.