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An effective solution of designing WIASoC with complex clock generation
Zhang ZP(张志鹏); Xie C(谢闯); Cui SP(崔书平)
作者部门工业控制网络与系统研究室
会议名称2014 International Conference on Industrial Electronics and Engineering (ICIEE 2014)
会议日期May 1-2, 2014
会议地点HongKong
会议录名称Industrial Electronics and Engineering
出版者WIT Press
2014
页码113-119
产权排序1
关键词Clock Generation C1ock Skew System On Chip Design-f1ow
摘要This paper describes a methodology used for the implementation flow of a system on chip circuit containing a complex clock design. The clock generation module contained 2 clock sources and 11 generated clocks. Many of them have interactive relationship. and the 2 clock sources generate the internal clocks in various modes. It uses the combination of bottom-up strategy and top-down strategy to accomplish the clock generation module implementation first, and then finish the whole chip design. This methodology of the solution makes the whole structure of the design distinct, saves a lot of iterative time, and reduces chip power consumption.
语种英语
文献类型会议论文
条目标识符http://ir.sia.cn/handle/173321/17417
专题工业控制网络与系统研究室
作者单位Shenyang Institute of Automation Chinese Academy of Sciences, Shenyang, China
推荐引用方式
GB/T 7714
Zhang ZP,Xie C,Cui SP. An effective solution of designing WIASoC with complex clock generation[C]:WIT Press,2014:113-119.
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