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题名: An effective solution of designing WIASoC with complex clock generation
作者: Zhang ZP(张志鹏); Xie C(谢闯); Cui SP(崔书平)
作者部门: 工业控制网络与系统研究室
会议名称: 2014 International Conference on Industrial Electronics and Engineering (ICIEE 2014)
会议日期: May 1-2, 2014
会议地点: HongKong
会议录: Industrial Electronics and Engineering
会议录出版者: WIT Press
出版日期: 2014
页码: 113-119
关键词: clock generation ; C1ock skew ; system on chip ; design-f1ow
摘要: This paper describes a methodology used for the implementation flow of a system on chip circuit containing a complex clock design. The clock generation module contained 2 clock sources and 11 generated clocks. Many of them have interactive relationship. and the 2 clock sources generate the internal clocks in various modes. It uses the combination of bottom-up strategy and top-down strategy to accomplish the clock generation module implementation first, and then finish the whole chip design. This methodology of the solution makes the whole structure of the design distinct, saves a lot of iterative time, and reduces chip power consumption.
语种: 英语
产权排序: 1
内容类型: 会议论文
URI标识: http://ir.sia.cn/handle/173321/17417
Appears in Collections:工业控制网络与系统研究室_会议论文

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