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基于HART C8PSK标准调制解调模块设计
周永忠1,2
Department工业控制系统研究室
Thesis Advisor杨志家
ClassificationTP311
KeywordHart C8psk 根升余弦 数控振荡器 联合仿真
Call NumberTP311/Z78/2008
Pages72页
Degree Discipline计算机应用技术
Degree Name硕士
2008-06-04
Degree Grantor中国科学院沈阳自动化研究所
Place of Conferral沈阳
Other AbstractHART C8PSK(Highway Addressable Remote Transducer Coherent 8-way sfhit key)协议是HART现场总线的第二代物理层协议,具有兼容HART现场总线第一代物理层协议HART FSK和速度更快的优点。调制解调模块是HART C8PSK协议中最重要的组成部分,本文根据HART C8PSK协议设计调制解调模块中的部分模块。 本文详细分析了HART C8PSK协议,完成了HART C8PSK调制解调模块的架构设计;搭建调制模块和解调模块中载波同步与码元同步算法级模型;实现调制模块和解调模块根升余弦滤波器并完成其功能验证。 模块的设计遵循以下过程:首先,进行模块原理模型的搭建和仿真,确定设计参数;然后,实现模块算法级模型,验证模块;最后,实现寄存器传输级(RTL)模型并验证模块。整个模块的运算采用定点运算形式。 HART C8PSK(Highway Addressable Remote Transducer Coherent 8-way sfhit key)协议是HART现场总线的第二代物理层协议,具有兼容HART现场总线第一代物理层协议HART FSK和速度更快的优点。调制解调模块是HART C8PSK协议中最重要的组成部分,本文根据HART C8PSK协议设计调制解调模块中的部分模块。本文在详细分析了HART C8PSK协议的基础上,完成了HART C8PSK调制解调模块的整体架构设计;在调制解调模块的行为级模型构建过程中,构建了调制模块和解调模块中载波同步模块与码元同步模块的行为级模型;在调制解调模块的RTL级实现过程中,设计并实现了调制模块和解调模块根升余弦滤波器,完成功能验证。在调制模块RTL级设计过程中,按照在根升余弦滤波器(RRC)的行为级模型仿真中设计的参数,选择多相结构实现根升余弦滤波器,降低了滤波器的工作频率;在解调模块的RTL级实现过程中,结合解调模块的特点,设计了一种节省查找表资源的FIR滤波器结构,两个模块中级联的根升余弦滤波器,很好的减小了码间干扰。在解调模块行为级模型构建过程中,设计了满足协议指标要求的载波恢复环路滤波器。利用根升余弦模块的行为级模型,使用MATLAB,Simulink和Modelsim联合搭建验证平台(TestBench),完成对RTL级根升余弦滤波器的仿真验证,简化了验证平台搭建的过程。本文设计实现了HART C8PSK调制解调部分模块,初步探讨了HART C8PSK模块设计过程,对今后HART C8PSK调制解调模块的设计有指导意义。 本文介绍了动态仿真验证方法、验证平台的搭建以及各个功能模块的验证方法和验证结果,证明设计的正确性。针对这里验证的特点使用MATLAB,Simulink和Modelsim联合搭建验证平台(TestBench),简化了验证平台搭建的过程。; HART C8PSK (Highway Addressable Remote Transducer Coherent 8-way Phase Shift Keying) Physical Layer Specification is the second generation Physical Layer Specification of HART Prototype that is compatible with HART FSK. Its raw data rate is 9.6kbps, faster than HART FSK. The module of modulation and demodulation is an important part of HART C8PSK specification. In this paper I realize some modules of HART C8PSK modem. Analyze the Physical Layer Specification of HART C8PSK communications protocols in detail, propose the architecture of modulator and demodulator. Build algorithmic module of modulator and algorithmic module of carrier synchronization and timing synchronization. Realize function simulation of the modulator and RRC at demodulator. In the process of design, we must follow the following steps. First build the theory model, design some parameters through simulation; second build the behavior model of module to verify the validity of the module; last realize the RTL (Register Translate Level) module. The realization of calculation is in fixed point. Module of state-control, scrambler, RRC in modulator and some other modules constitute the modulator. The scrambler is realized according to IUT-T v.27ter. Design and realize Root Raised Cosine Filter (RRC) in modulator. RRC in demodulator, carrier synchronization and timing synchronization are very important parts in demodulator. According to the circumstance of demodulator, design a structure which needs less Look-Up table and realize RRC in demodulator in it. I propose a new method for designing the carrier synchronization circuit’s filter according to the specification and design the filter by the method. Simplify the design of number control oscillator (NCO) according to the circuit of carrier synchronization. Analyze and simulate the arithmetic of timing synchronization in the specification. HART C8PSK (Highway Addressable Remote Transducer Coherent 8-way Phase Shift Keying) Physical Layer Specification is the second generation Physical Layer Specification of HART Prototype that is compatible with HART FSK. Its raw data rate is 9.6kbps, faster than HART FSK. The module of modulation and demodulation is an important part of HART C8PSK specification. In this paper I realize some modules of HART C8PSK modem. Analyze the Physical Layer Specification of HART C8PSK communication protocols in detail, propose the architecture of modulator and demodulator. In the processing of building algorithmic module of modulator and demodulator, Build algorithmic module of modulator and algorithmic module of carrier synchronization and timing synchronization in demodulator. In the processing of building RTL (Register Transfer Level) module of modulator and demodulator, Realize function simulation of the modulator and RRC at demodulator. In the processing of realizing RTL model of modulator, Design and realize Root Raised Cosine Filter (RRC) according to the parameters got from the algorithmic module; In the processing of realizing RTL model of demodulator, design a new structure of FIR(Finite Impulse Response ) filter which can save resource of Look Up Table. The serial RRC filters designed can eliminate the ISI well. In the processing of building algorithmic model of demodulator, design the carrier synchronization circuit’s filter according to the specification. Simulate RRC filter of RTL through cosimulation TestBench which is built under the environment of MATLAB and Modelsim that simplifies the process of building TestBench. In the article I realize some modules of HART C8PSK modulator and demodulator, study the design processing of HART C8PSK module, which can guide the following design.
Language中文
Contribution Rank1
Document Type学位论文
Identifierhttp://ir.sia.cn/handle/173321/484
Collection工业信息学研究室_工业控制系统研究室
Affiliation1.中国科学院沈阳自动化研究所
2.中国科学院研究生院
Recommended Citation
GB/T 7714
周永忠. 基于HART C8PSK标准调制解调模块设计[D]. 沈阳. 中国科学院沈阳自动化研究所,2008.
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