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题名: The testing of multiple RAM Cores in Soc system
作者: Wang Y(汪莹) ; Wang H(王宏)
作者部门: 工业控制系统研究室
会议名称: 8th International Conference on Solid-State and Integrated Circuit Technology. ICSICT '06
会议日期: October 23-26, 2006
会议地点: Shanghai, China
会议主办者: IEEE
会议录出版者: IEEE
会议录出版地: New York
出版日期: 2006
页码: 2148-2150
收录类别: EI
摘要: The development of the sub-micron technology makes it possible that the manufacturer of ASIC integrates IP into a single chip. The embedded memory is difficult to test because of the compact construct. Measurer, BIST and processor-based are the mainly three methods. The BIST method decreases the test time by sacrificing the area. The BIST has been the main test method due to the better performance. The cost of the area and pad is large if every memory possesses a BIST controller in the system. The paper adopts a BIST controller to control dozens of memories. The method has the advantage of better flexibility, shorter time and lower area. The paper researches the test strategy for several distributed different sizes and algorithms memories. Only a microcode-based controller is used. The code for different test algorithm is stored in ROM. The controller disposes the symmetry structure of the algorithm. If the two sections have reverse address order, data mode and compare bit, the recurrence instruction and the recurrence register run a specific program by reverse address order, data mode and compare bit again. The memories possessing the same algorithm can be test simultaneously by the synchronous signal. A wrapper is added to every memory for communication between the memory and controller. The results indicate that the controller has better flexibility, shorter test time, lower area and simpler test instructor set
语种: 英语
产权排序: 1
内容类型: 会议论文
URI标识: http://ir.sia.cn/handle/173321/8142
Appears in Collections:工业信息学研究室_工业控制系统研究室_会议论文

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Recommended Citation:
汪莹; 王宏.The testing of multiple RAM Cores in Soc system.见:IEEE .,New York,2006,2148-2150
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