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题名: A CMOS hysteresis undervoltage lockout with current source inverter structure
作者: Zhang C(张超) ; Yang ZJ(杨志家) ; Zhang ZP(张志鹏)
作者部门: 工业信息学研究室
会议名称: 2011 IEEE 9th International Conference on ASIC (ASICON 2011)
会议日期: October 25-28, 2011
会议地点: Xiamen, China
会议主办者: IEEE Beijing Sect.
会议录: Proceedings of the 2011 IEEE 9th International Conference on ASIC (ASICON 2011)
会议录出版者: IEEE
会议录出版地: Piscataway, NJ, USA
出版日期: 2011
页码: 918-921
收录类别: EI
ISBN号: 978-1-61284-192-2
摘要: This paper describes a simple architecture and low power consumption undervoltage lockout (UVLO) circuit with hysteretic threshold. The UVLO circuit monitors the supply voltage and determines whether or not the supply voltage satisfies a predetermined condition. The under voltage lockout circuit is designed based on CSMC 0.5um CMOS technology, utilizing a relatively few amount of circuitry. It is realized with a current source inverter. The threshold voltage is determined by the W/L ratio of current source inverter and resistor in reference generator. The hysteresis is realized by using a feedback circuit to overcome the bad disturbance and noise rejection of the single threshold. Hysteretic threshold range is 40mV. The quiescent current is about 1uA at 3V supply voltage,while the power of circuit consumes only 3uW.
产权排序: 1
内容类型: 会议论文
URI标识: http://ir.sia.cn/handle/173321/8296
Appears in Collections:工业信息学研究室_会议论文

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Recommended Citation:
张超; 杨志家; 张志鹏.A CMOS hysteresis undervoltage lockout with current source inverter structure.见:IEEE .Proceedings of the 2011 IEEE 9th International Conference on ASIC (ASICON 2011),Piscataway, NJ, USA,2011,918-921
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