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题名:
Writing a RVM-Compliant AHB Master Transactor
作者: Yang ZJ(杨志家); Zhang YF(张玉峰); Li SG(李肃刚); Chen, Jason C.
作者部门: 工业控制系统研究室
会议名称: 2005 SNUG论文集
会议地点: Beijing
会议主办者: Synopsys
会议录: 2005 SNUG论文集
会议录出版者: Synopsys
会议录出版地: Beijing
出版日期: 2005
关键词: AHB Master ; DesignWare VIP ; RVM base class ; transactor ; rvm_xactor
摘要: The use of AMBA-based buses is ubiquitous in today’s System On Chips (SoC). Verification IPs (VIP) are effective in generating stimuli for block-level, subsystem-level, and top-level testbenches. The reference verification methodology (RVM) and its base class library for Vera help verification engineers to build a testbench that enables constrained random verification and promotes re-use. Keeping the transactors in an RVM style makes them have the same look and feel and consequently make them easier to use (e.g. when writing tests). This paper discusses how an RVM compliant AHB master transactor is designed using the DesignWare AHB Master VIP and demonstrates how to configure it for the testbench and how to create test stimuli using the transactor
语种: 英语
产权排序: 1
内容类型: 会议论文
URI标识: http://ir.sia.cn/handle/173321/9196
Appears in Collections:工业信息学研究室_工业控制系统研究室_会议论文

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Recommended Citation:
Yang ZJ,Zhang YF,Li SG,et al. Writing a RVM-Compliant AHB Master Transactor[C]. 2005 SNUG论文集. Beijing.Writing a RVM-Compliant AHB Master Transactor.
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