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题名: HART PSK 物理层关键技术研究
其他题名: Research on Key Technologies of HART PSK Physical Layer
作者: 金郑华
导师: 王宏 ; 杨志家
分类号: TN915.04
关键词: 信道建模 ; 同步 ; 信道估计与均衡 ; 自动调制设别 ; HART PSK调制解调器
索取号: TN915.04/J67/2012
学位专业: 机械电子工程
学位类别: 博士
答辩日期: 2012-04-25
授予单位: 中国科学院沈阳自动化研究所
学位授予地点: 中国科学院沈阳自动化研究所
作者部门: 工业控制网络与系统研究室
中文摘要: HART通信技术是工业自动化最重要的现场总线协议之一,该技术在广泛使用的4-20mA模拟通信环路上叠加小幅数字载波信号进行半双工数字通信。HART PSK物理层在现有的FSK调制解调基础上新增了C8PSK调制解调,可将HART数字通信效率提高10倍。但C8PSK调制解调本身复杂,信号传输时容易发生畸变,而且HART对功耗要求严格,因此到目前为止,HART C8PSK调制解调器始终未能得到实际应用。本文以HART PSK数字接收机为主要研究对象,以信道特性为基础,研究了接收机中关键模块的低功耗和高性能算法。论文主要工作和创新如下:1.首先分析了HART PSK物理层实现高性能和低功耗数字载波通信所需解决的关键问题,并论述了相关技术研究现状和存在的问题。详细论述了HART PSK最佳接收准则,最佳接收机结构以及相关模块算法的特点。2.建立HART PSK物理层信道的理论传输模型和分段电路简化模型,通过仿真和实际测量,对比验证了两种模型的精确性和一致性。进一步研究了信道的频率特性曲线,脉冲响应特性,以及信道幅频响应和相频响应的对应关系。并分析了信道中主要噪声源的特性,给出了噪声合并计算方法和信道合成噪声的特性。3.同步是C8PSK载波信号相干解调的关键,常规算法很难满足低功耗和快速收敛要求,为此提出将C8PSK同步分成捕获和跟踪两步实现,研究新同步算法提高同步偏差估计速度和精度,并改进同步补偿环路控制策略来提高同步系统稳定速度。对于同步捕获,提出两种快速数据辅助(DA,Data-Aided)同步算法,使用简单加法窗来实现同步快速稳定,并进一步分析它们的本质,给出了推广算法。对于同步跟踪,研究了2倍过采样率判决反馈 (DD,Decisions Directed)低功耗同步跟踪算法,该算法使用自噪声补偿提高参数估计精度;同时DD算法的低速率输入使得均衡器工作频率降低,大幅降低了其功耗。在载波补偿上,采用8象限判决和小数相角线性近似策略,改进了常规旋转数字计算(CORDIC,Coordinate Rotation Digital Computer)算法,使得同等相角精度下迭代计算次数减半;分析了低功耗数字锁相环 (DPLL,Digital Phase Lock Loop)的大时滞特性,提出了基于采样控制原理的大时滞DPLL控制策略。在位定时补偿上,利用一阶自适应Kalman环路滤波算法解决了定时跟踪环路的延时和噪声干扰问题。4.信道估计和均衡等自适应接收模块功耗很大,本研究通过多功能模块和均衡器结构改进,提高系统性能,降低系统功耗。研究了HART PSK前导码信号联合时频分析方法,并给出了时频分析稳定速度最快,稳态波动最小的最小均方误差 (MMSE,Minimum Mean Square Error)低通滤波策略。基于时频分析结果、信道传输特性和两种前导码信号的频谱,提出一种简单的信道估计、自动调制识别和自动增益控制联合算法。根据信道传输特性和信道估计输出,设计了一种基于CSD(Canonic Signed Digital)编码的预置式分数间隔均衡器,大幅减小了均衡器每次计算的功耗。5.研究了FSK和C8PSK一体化调制解调器设计方案;提出了一种复用C8PSK接收机结构的简单FSK解调算法;并提出C8PSK两倍采样信号的码元判决算法,与码元速率采样的最佳判决相比,可以实现2dB SNR改进。对HART PSK物理层电路系统设计给出了3种不同层次的验证策略,并对其功耗进行了详细分析,验证和分析结果证明了本研究的HART PSK物理层电路具有较高的性能和较低的功耗。
英文摘要: HART enhances the widely used traditional 4-20 signaling loop by simultaneously adding little carrier signal to achieve half-duplex digital communication, regarded as one of the most important field-bus protocols in industrial automation. HART PSK physical layer (PHL) introduces C8PSK modulation on the basis of the existing FSK modulation, and can provide 8-10 faster digital communication rates than the existing HART. C8PSK signal is a more much complex modulated and can be distorted by the channel, while HART has strict requirement on low power. HART PSK MODEM has never been applied in practice. Base on the channel characteristics, we focus our attention on receiver part of the HART PSK PHL circuits and study key module algorithms in the reeiver to achieve low power and high performance requirements. The main contents and innovation points of this paper are as follows: 1. We conclude the key technologies involved in high performance and low power circuit design for HART PSK PHL, and related research achievements are introduced. We discuss the optimal reception criteria, the structure of the optimal receiver, and the algorithm characteristics of the related modules. 2. We develop theoretical transmission model and sectioned circuits simplified model of HART PSK channel. Simulations and the test data show consistency and accuracy of the two models. Using the channel models simulations, we study the frequency response, impulse response and relationships between the amplitude –frequency response and the phase-frequency response. The main noises in the channel and their characteristics are analyzed; their combination algorithms and consolidated characteristic are introduced. 3. Sychronzation is a key problem for C8PSK demodulation, and ordinary algorithms are difficult to meet the low power and fast convergence requirements. Two step, acquisition and tracking, are proposed for C8PSK Sychronzation. New algorithms and control strategies are put forward to improve the precision and speed of the synchronization system. For acquisition, fast data-aided (DA) algorithms are put forward, using addition window to make synchronizer stable fast, then their extended algorithms are presented based on their essence analysis. For tracking, we research 2 oversample rate decisions directed (DD) algorithms, using self-noise compensation to improve the precision of the parameters’ estimation. At the time low data rate of the DD algorithms decrease the equalizer operating frequency, reduing its power greatly. In carrier compensation, based on 8 quadrants judgment and fractional phase linearity approximation, we modify ordinary CORDIC algorithm, halving the iterative calculation while maintain the same precision; we analyze the big delay involved in the DPLL, and we propose a control strategy that based on sampling control theory to conquer the loop big delay. In timing compensation, an adaptive one order Kalman filter algorithm is put forward to conquer the noise and delay of the timing loop. 4. Adaptive receiveing modules, such as channel estimation and equalization, are high power consuming, multifunction module and new structure equalizer are proposed to improve profermance and low power. We study joint time-frequency analysis algorithm for HART PSK preambles signal, and deduce its optimal MMSE low pass filtering strategy to make time-frequency analysis converge fast and jitter little in stable state. Based on the time-frequency analysis and channel characteristics, a simple joint algorithm for channel estimation, automatic modulation classification (AMC) and AGC is proposed. Based on channel characteristics, AMC, and channel estimation, we propose a CSD coded preset fractional equalizer, reducing to power consumption greatly per one equalizing computation. 5. We put forward an incorporated HART PSK MODEM. A new FSK demodulation algorithm is put forward, reusing the resource of the C8PSK demodulator. A new symbol judgment algorithm based on 2-oversample rate baseband signal is proposed; comparing with ordinary optimal judgment algorithm, 2 dB SNR improvements can be achieved. We propose 3 different levels verification strategies for HART PSK PHL circuits, and summarize the computational complexity involved in the highest power state. The computational complexity comparison and verification result prove that our research can provide solutions for HART PSK PHL design with high performance and low power dissipation.
语种: 中文
产权排序: 1
内容类型: 学位论文
URI标识: http://ir.sia.cn/handle/173321/9331
Appears in Collections:工业控制网络与系统研究室_学位论文

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金郑华.HART PSK 物理层关键技术研究.[博士学位论文].中国科学院沈阳自动化研究所.2012
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