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题名: 高速PLC专用指令集处理器的研究
其他题名: Research of high Speed PLC ASIP
作者: 曾舒婷
导师: 杨志家
分类号: TP332.1
关键词: PLC ; 专用指令集 ; 专用指令集处理器 ; RISC体系结构 ; 四级流水线
索取号: TP332.1/Z22/2011
学位专业: 计算机技术与应用
学位类别: 硕士
答辩日期: 2011-05-27
授予单位: 中国科学院沈阳自动化研究所
学位授予地点: 中国科学院沈阳自动化研究所
作者部门: 工业信息学研究室
中文摘要: 随着工业控制现场对实时性需求的日益增长,高速可编程控制器的研究显得十分重要。而可编程控制器是以微处理器为核心的新型工业自动控制装置,这使得提高可编程控制器微处理器性能成为研究高速可编程控制器的关键。该高速PLC专用指令集处理器采用自主设计的PLC专用指令集,并通过分析PLC程序执行特征、指令类型、数据类型及其存取模式,设计出有利于PLC程序快速执行的PLC专用指令集处理器体系结构。 该高速PLC专用指令集处理器采用自主设计的PLC专用指令集,符合PLC指令特征,相对传统的PLC处理器可减少执行的指令数。通过分析符合IEC 61131-3标准的PLC指令表程序的指令种类及各类指令使用频率,得出PLC程序以布尔指令为主,通过调用功能及功能块来完成PLC控制任务。据此,该 PLC专用指令集主要分为位逻辑运算指令集和功能块指令集。通过分析布尔指令在PLC梯形图程序中的特征,提出了可跳转位逻辑指令集,提高了PLC布尔指令的执行速度。 依据PLC专用指令集,该PLC专用指令集处理器采用32位RISC体系结构。由于PLC程序反复顺序执行的特征,该PLC专用指令集处理器无需高速缓存。依据PLC数据以位数据为主,将其寄存器组采用位编址模式。依据PLC功能块并行执行的特征,设计功能块寄存器组,利于功能块指令的执行。由于可编程控制器对数据存取频繁,该高性能PLC专用指令集处理器采用哈佛总线结构,其数据寻址方式采用存取器直接寻址、寄存器直接寻址方式及直接寻址方式,提高了数据存取速度。 依据PLC专用指令集,该高速PLC专用指令集处理器的位处理器可加速PLC布尔运算;为满足PLC程序对功能块调用的需求,其功能块单元采用并行模式,即同类或不同类功能块都可并行执行;由于输出结果分别保存在寄存器组及数据存储器内,则结果存储和回写阶段可合并为一个阶段,采用四级流水线,提高PLC指令的执行速度。 该高性能PLC专用指令集处理器的系统功能仿真及综合正确,并在FPGA上成功实现。
英文摘要: With the increasing real-time demand of the industrial control, the research of a high speed programmable logic controller seems very important. The microprocessor of PLC is the core of the new mechanism, and automatically controls the performance of PLC, which makes the study of a microprocessor becomes the pivotal part for performance improvement. The High speed of the PLC ASIP adopts the design of the PLC special instruction set, and adopts application of the PLC ASIP architecture for the rapid implementation through the analysis of the character of PLC instruction or data type and access. The rapid PLC ASIP uses the design of the PLC special instruction set. In accordance with instructions relative to the PLC, the PLC processors might reduce the number of instructions. The analysis of classes of PLC instructions according to IEC 61131-3 standard and the frequency of PLC instructions use, we can see the PLC program mostly uses instructions in Boolean, and calls for a specific function or function. Basis of the PLC special instruction set, the PLC ASIP uses 32-bit RISC architecture. According to the orderly execution of PLC program, the cache needn’t to be used for the PLC ASIP. The bit address of register is designed for bit data type. On the functions of the PLC in parallel, the register of function is designed for function instructions. For the frequently data access of PLC, the high-performance PLC ASIP uses the structure of the Harvard. The memorydirect accessing and register direct accessing and direct accessing are adopted to address to improve the speed of data access. According to the PLC special instruction set, the PLC special instruction set up a bit processor to rapid PLC operation; to meet application to function of the PLC, the function unit with the same or different kinds of functions can be implemented in parallel; as the output is held in a register or data memory, and the store stage and write back stage are merged as a stage; and make use of the PLC four pipelines for the instruction enforcement speed. The report of the PLS ASIP system function test and synthesis is right. And the PLC ASIP is implemented on the FPGA.
语种: 中文
产权排序: 1
内容类型: 学位论文
URI标识: http://ir.sia.cn/handle/173321/9344
Appears in Collections:工业信息学研究室_学位论文

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