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题名:
面向工业现场总线系统的SoC关键技术研究与设计
其他题名: The SoC Technology Research and Design for Industrial Fieldbus System
作者: 杨志家
导师: 王宏
分类号: TP273
关键词: 分布式控制系统 ; 现场总线 ; 协议芯片 ; 低功耗设计 ; 硬件调度器 ; 安全仪表系统
索取号: TP273/Y29/2011
学位专业: 机械电子工程
学位类别: 博士
答辩日期: 2011-11-25
授予单位: 中国科学院沈阳自动化研究所
授予地点: 沈阳
作者部门: 工业信息学研究室
摘要: 工业自动化技术随着微电子、计算机、网络和控制理论的发展,已经发生了巨大的变化。今天覆盖从工段、车间、工厂及企业的大规模智能化现场总线控制系统得到了全面的应用。现场总线是指连接测量、控制仪表和设备,如传感器、执行器和控制器的全数字化、串行、双向的通信系统。它不仅采用了全数字化、串行、双向的通信系统,而且具有将控制任务分散到现场设备当中的能力,是一种全分布式数字化智能控制系统。 虽然现场总线控制系统在近些年得到了广泛的应用,但是仍然存在:协议的复杂性;调度的确定性;响应的实时性;设备低功耗的本安特性;系统的高可靠性等进一步优化的研究问题。本文结合集成电路设计的新方法和新技术,针对上述问题,开展了面向现场总线系统的SoC关键技术研究,取得了如下成果: 1、分析了典型的工业现场总线技术,明确了现场总线系统的总体需求和各层功能。采用PBD方法,建立了现场总线技术的系统功能模型,包括:应用软件模型、服务软件模型、时间触发模型、事件触发模型、数据存储模型。完成了现场总线SoC系统的软硬件划分和模型映射,同时给出了现场总线SoC芯片的架构设计方案、内存映射方案、时间域划分方案。并通过三个验证测试阶段不断递进,完成了系统集成仿真验证测试、基于FPGA的快速原型系统验证测试、基于样片的系统在线验证测试,最后给出了MPW样片的在线测试结果。验证了系统架构和各个模块设计的正确性。 2、分析了以事件触发为主的现场总线技术,明确了该类现场总线从站各个分层的功能。结合集成电路功耗模型和低功耗设计方法,抛弃了传统的基于微序列机的设计理念,提出了基于事件触发模型设计低功耗协议处理器IP的设计思想,将原语作为事件并完全采用硬件设计完成事件处理和报文操作。该低功耗协议处理器IP通过了标准协议全部测试集的测试,并成功完成了基于0.35um工艺的硅验证测试,测试结果表明基于事件触发的设计方法在低功耗和响应时间延迟方面具有明显优势。 3、针对现场总线仪表内功能块应用和链路调度实时性的矛盾,提出了一种基于时间触发模型的硬件逻辑实现链路调度器的设计方法。首先分析了作为链路活动调度器的主要功能和触发工作模式,总结了链路调度令牌的种类和时间触发基准,定义了1/32ms、Octet Time、1ms三类时间基准触发器和它们的优先级。将1/32ms时间基准触发器分配给了CD强制调度令牌,优先即最高。将Octet Time时间基准触发器分配给了PT授权令牌和PN探测令牌。将1ms时间基准触发器分配给了TD时间发布令牌,优先级最低。然后配合时间基准触发器为每一种令牌分配了一个报文缓冲队列,用来缓存由时间基准触发器控制输出的令牌。最后设计了硬件加载、解析、处理的链路调度处理器HSKernal模块及它们之间的控制与数据传输,并完成了整个现场总线系统的硬件链路调度器。该方法有效地将现场设备的CPU从数据链路层调度活动中解放出来,用户可以利用释放出来的处理能力进行复杂的功能块运算处理等事务。最后给出了硬件链路调度器的实时性分析和触发抖动分析,结果表明该硬件链路调度器具有比软件实现的链路调度器更好的实时性和更小的抖动。 4、针对现场总线的安全和可靠性问题,提出了一种增强型双通道的现场总线通信控制器解决方法,依托本单位前期研究设计的单通道现场总线通信控制器FBC0409,研究设计了支持双通道具有冗余功能的通信控制器FBC0409D,在FBC0409D上集成了两路接收控制器和两路发送控制器,同时设计了双通道监视状态控制逻辑模块,支持冗余硬件测试功能,在不同用况下可以实现安全性和可靠性的应用。然后根据安全仪表系统的可靠性和安全性概念和指标,分析了基于双通道通信控制器FBC0409D的FF-SIS系统,分析结果证明了与采用单通道通信控制器的FF-SIS在可靠性方面有明显的提升,平均故障前时间可以达到之前的4.5倍,同时采用双通道通信控制器FBC0409D方案设计的现场总线设备的安全完整性等级可以达到SIL3。
英文摘要: With the development of microelectronics, computers, networks and control theory, industrial automation technology has made greatly achievements. Today, large-scale intelligence fieldbus control system covering the floors, plants, factories and enterprises has been fully applied. Fieldbus is the two-way communication system for measurement, control instrumentation and equipment such as sensors, actuators and controllers, all-digital, serial. It not only uses all-digital, serial, two-way communication system, but also has the ability to distribute control to field devices, which is an all-digital intelligent distributed control system. Although the fieldbus control system has been widely used in recent years, the following problems are still there: the complexity of protocol, scheduling determinacy, real-time response, equipment’s low power consumption for intrinsic safe, and the system's high reliability. In this dissertation, to address the problem, with a new integrated circuit design method and new technologies, a fieldbus system SoC key technology research has been carried out, and the following results have been achieved. 1, Typical industrial fieldbus technology is analyzed, and the fieldbus system requirements and layers functions are specified. The PBD method is used to establish the fieldbus system functional model, including: application software model, services software model, time-triggered model, event-triggered model, data storage model. Hardware and software partition of SoC system and model mapping is completed, and the architecture of fieldbus SoC chip design, the memory mapping scheme, the time domain scenario are given. And through three progressive stages of validation testing, system integration simulation verification test, FPGA-based rapid prototyping system verification test, in loop verification test system based on sample SoC chip are completed. Final test results of MPW-chip are given, and the correctness of system architecture and each module are verified. 2, Event-triggered fieldbus technology is analyzed, and this kind of fieldbus slave functions of each layer is specified. Low-power integrated circuit power consumption model and design approach are combined, and the traditional micro-sequencer based design is abandoned. A model based on event-triggered model design low-power protocol processor IP is proposed, and the primitive is regarded as events and completely hardware design event handling and message completion of operation is adopted. The low-power protocol processor IP passed through the standard protocol full test set test, and the process based on 0.35um silicon validation test is successfully completed. The test results show that the design method based on event triggers in low power consumption and response time delay have obvious advantages. 3, For the fieldbus function blocks within real-time applications and link scheduling conflicts, a model based on time-triggered hardware logic is proposed to achieve link scheduler design. Link Active Scheduler's main functions and trigger mode are analyzed, and the token type and link scheduling time-triggered time basis are summed up. A 1/32ms, Octet Time, 1ms time base three types of triggers and their priority are defined. 1/32ms time base trigger mandatory schedule is assigned to the CD token, which is the highest priority. The Octet Time is allocated to the time base trigger PT authorization token and PN detect token. The 1ms time base trigger release time is assigned to the TD token, the lowest priority. Then with the time base trigger for each token is assigned a message buffer queue, for caching the output message token from the time base trigger control. The hardware modules of loading, parsing, processing, scheduling processor HSKernal and their control and data transfer signals between the modules are finally desinged, and the fieldbus system hardware link scheduler is completed. This method is effective in the field devices of the CPU from the data link layer scheduling activities, so that users can use the released capacity to handle complex operations such as function block application. Finally, the hardware link scheduling for real-time analysis and trigger jitter analysis are given. The results show that the hardware link scheduler is better than the software link scheduler and has smaller jitter. 4, For fieldbus safety and reliability problems, we propose a dual-channel enhancement-type fieldbus communication controller solution, relying on the design of a single-channel fieldbus communication controller FBC0409 in the preliminary study. A dual-channel communications controller is studied and designed with redundancy FBC0409D. The FBC0409D integrates two transmitting controllers and two receiving controllers. In the mean while, a dual-channel monitoring state control logic module is designed, supporting the tests by reduant hardware feature, which can be used in different cases and can achieve safety and reliability. Then based on the reliability and safety concepts and indicators of safety instrumented systems, dual-channel communications controller FBC0409D of FF-SIS system is analyzed. The results demonstrate that with the use of single-channel communication controller FF-SIS the reliability is improved significantly, and the mean time to failure can be achieved as 4.5 times high as before. And using dual-channel communications controller FBC0409D design of fieldbus devices can achieve safety integrity level SIL3.
语种: 中文
产权排序: 1
内容类型: 学位论文
URI标识: http://ir.sia.cn/handle/173321/9360
Appears in Collections:工业信息学研究室_学位论文

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Recommended Citation:
杨志家. 面向工业现场总线系统的SoC关键技术研究与设计[D]. 沈阳. 中国科学院沈阳自动化研究所. 2011.
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